Circuit Complexity

Multi-layer Fine Line Circuits
Through Hole (Castellation) Metallization
Filled and Plugged Hole Metallization
Direct Chip and Wire Bonding
Chip Scale Packaging (CSP)

Substrates:

96% Alumina
Aluminum
Stainless Steel
Polymer
Al2O3, ALN

Conductor Materials:

Pt/Ag, Pt/Au, Pd/Ag, Au, Ag, Pt/Pd/Ag

Resistor Materials:

Ruthenium Oxide

Line Definition:

0.025mm to 0.050mm (0.001″ to 0.002″) – Fine Line
0.25mm (0.010″) – Standard

Resistors:

Range: 0.1Ω to 15 GΩ
Tolerance: 0.05% (absolute)
TCR: ±100PPM/°C or better

Dielectric Constant:

1 MHz: 9.3 (For 96% Alumina)
1 GHz: 9.2 (For 96% Alumina)

Packages:

Conformal coating, SIP, DIP, PGA, TO, Flat pack, BGA

Test specifications:

MIL-STD, DIN, EIAJ, and JEDEC etc

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